Achieving chip-to-chip and intra-chip photonic interconnects in Silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) and in BiCMOS presents an extreme challenge to active photonic devices because the energy used in the optical communication link of such devices is desirably less than 100 femto Joules (10−15 Joules) per data bit transmitted. This is the energy dissipated by the coupled photonic link comprised of a continuous wave laser, a fast modulator and a photodetector. As devices become optimized, this energy should be “down-scalable” year-by-year. This link constraint, may also be expressed in terms of milliwatts per Gigabit of communicated data and is a key to making photonic interconnects superior to copper interconnects. A solution to this photonic link problem resides in a nano photonic approach in which the on-chip electrically pumped lasers, the electro optical modulators, and the photo detectors all are (1) waveguide devices with a very small footprint, (2) devices with an ultra small mode volume, (3) devices with very good overlap between the fundamental mode and the active region of the device, and (4) devices with lateral P and N regions having lower mode loss than vertical P and N layers. This invention teaches the achievement of such devices in a Silicon-on-insulator platform that is fully compatible with state-of-the-art commercial CMOS processing. The invention also teaches the use of nanometer-scale optical resonators to enhance device performance and provide high quantum efficiency (wall-plug efficiency) that is essential to the interconnect application. The achieved devices are inherently fast, on the order of 10 Gigabits per second.
The prior invention of R. A. Soref as disclosed in U.S. Pat. No. 5,838,870, (Ref. 1) teaches the achievement of nano photonic devices that are suitable for intra- and inter-chip communication (FIG. 4 of the '870 patent). [Reference 1, (Ref. 1) etc., is listed at the close of this document.]. These devices however have several drawbacks. Specifically, (1) the vertical P-intrinsic-N (PIN) resonator within the one dimensional (1D) photonic-crystal waveguide includes a metalized air-bridge top contact that is not acceptable for optoelectronic integration in a CMOS manufacturing facility, (2) the P- and N-doped layers on the top and bottom of the waveguide, respectively, induce unwanted propagation losses, and (3) the active material chosen in the patent consists of “bulk” Silicon or Silicon quantum wells with high barriers, or SiGe quantum wells, i.e., devices that are difficult to make. With knowledge gained during the almost ten years ensuing since the '870 patent was filed, I now know that this set of materials is not optimum for the required lasing, modulation, and detection functions. For example, in “bulk” Silicon the optical gain produced during high carrier injection is slightly less than the free carrier absorption encountered.
The use of superior materials, all within periodic table group IV, are taught in the present photonic invention. I find that elemental Germanium, Ge, as well as alloys in the ternary family of Silicon, Germanium and Tin, SiGeSn, are preferred for the purposes of the achieved Franz-Keldysh modulation, for strong absorption within a detector, and for inherent gain that is larger than the induced free-carrier absorption. When embedded in Silicon waveguides, these active-materials create nano-hetero diodes such as Si/Ge/Si and Si/GeSn/Si in the present invention. Thus to summarize, the present invention offers significant improvement over the '870 patent in PIN integration, in waveguide transparency and in better-performing active devices.